International Journal of Information Technology and Computer Science (IJITCS)
IJITCS Vol. 3, No. 4, 8 Aug. 2011
Cover page and Table of Contents: PDF (size: 193KB)
NoC Research and Practice: Design and Implementation of 2×4 2D-Torus Topology
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Author(s)
Xingang Ju
1,*
Liang Yang
1
Index Terms
Network on Chip, On-chip communication, topology, routing node, routing algorithm, uninterrupted operation
Abstract
Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, it introduces the basic concept and architecture of the NoC, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format, routing and arbitration. Secondly, routing nodes coding, routing algorithm and node degree routing direction are designed. Thirdly, the programming and simulation of 2×4 NoC interconnection architecture are designed, and it achieves uninterrupted operation. The result shows the correctness of the interconnection architecture design. Finally, it chooses XC4VSX55-12ff1148 of vertext 4 to synthesize, the maximum frequency can up to 268 MHz, which provides foundation of subsequent research and application.
Cite This Paper
Xingang Ju, Liang Yang, "NoC Research and Practice: Design and Implementation of 2×4 2D-Torus Topology", International Journal of Information Technology and Computer Science(IJITCS), vol.3, no.4, pp.50-56, 2011. DOI:10.5815/ijitcs.2011.04.08
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