International Journal of Modern Education and Computer Science (IJMECS)

IJMECS Vol. 8, No. 6, Jun. 2016

Cover page and Table of Contents: PDF (size: 170KB)

Table Of Contents

REGULAR PAPERS

Hackathon for Learning Digital Theology in Computer Science

By Emmanuel Awuni Kolog Erkki Sutinen Eeva Nygren

DOI: https://doi.org/10.5815/ijmecs.2016.06.01, Pub. Date: 8 Jun. 2016

Hackathon is an event where programmers and subject field specialists collaborate intensively in teams with the ultimate aim to create and design fresh ICT (information and communication technology) based solutions to a given task in a limited time. In this study, we analyzed students‟ perceptions and experience in a hackathon where they were to design a concept for an application aimed at people that are preparing for their own death. The hackathon was part of a Digital Theology (DT) course at the university for Computer Science (CS) students. 12 participated students were divided into three groups, where an assignment was presented to the groups to brainstorm and create a mock-up artefact suitable to tackle the challenge (assignment). By collecting data through questionnaires and interviewing the participants, we applied descriptive statistics rather than exploring into inferential statistics to analyze the data due to the limited number of students. In the end, the results show that the use of hackathon helped in achieving the learning goals of DT.The students expressed their satisfaction in the fact that it provided them with motivation to learn through practice. Also, students agreed that the event helped them to think collaboratively for a refined ideas. The overwhelming satisfaction expressed by the students goes to confirm that hackathon brings out the best creative skills from people through problem-solving.

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Semantic Annotation of Pedagogic Documents

By Benyahia Kadda Lehireche Ahmed

DOI: https://doi.org/10.5815/ijmecs.2016.06.02, Pub. Date: 8 Jun. 2016

To teach, teacher needs help for sharing these educational documents, and especially his knowledge. We present an approach to overcome the difficulty of sharing educational materials and facilitate access to content; we describe semantically these documents to make them accessible and available to different users. The main idea in our annotation approach is based on: (1) Identify key words in a document, to have a good presentation of the document, we extract the candidate words by applying a weighting process and another process using similarity measure, These keywords candidates are reconciled with ontology to determine the appropriate concepts. (2) As document reference generally other documents, we propagate the annotations of references for citing document.
(3) A process of validation will be applied each time an annotation is added in order to keep the coherence of the base of annotation.
After evaluation with several types of pedagogic documents, our approach achieved a good performance; this suggests that teachers can be greatly helped for the semantic annotation of their pedagogical documents.

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Novel Reversible DS Gate for Reversible Logic Synthesis

By Shaveta Thakral Dipali Bansal

DOI: https://doi.org/10.5815/ijmecs.2016.06.03, Pub. Date: 8 Jun. 2016

Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. As our day to day life is demanding more and more portable electronic devices, challenging focus on technology is demanding great system performance without any compromise in power consumption. It is obvious to find tradeoff between processing power and heat generation. As decreased processing speed leads to reduced power consumption but obviously compromise in performance is not acceptable for sophisticated applications. Thus power consumption is a prime target now days. Needless to say, researchers will now look at reversible logic in this vein. Primitive component of reversible logic synthesis are reversible logic gates .Thus it is very important for a new researcher to look into extensive literature survey of reversible logic gates. Many papers have been reported with review of reversible logic gates. This paper aims on updates in reversible logic gates and propose a novel reversible DS gate which will be stepping stone in design and synthesis of any complex reversible logic based synthesis.

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Empirical Analysis of HPC Using Different Programming Models

By Muhammad Usman Ashraf Fadi Fouz Fathy Alboraei Eassa

DOI: https://doi.org/10.5815/ijmecs.2016.06.04, Pub. Date: 8 Jun. 2016

During the last decade, Heterogeneous systems are emerging for high performance computing [1]. In order to achieve high performance computing (HPC), existing technologies and programming models aims to see rapid growth toward intra-node parallelism [2]. The current high computational system and applications demand for a massive level of computation power. In last few years, Graphical processing unit (GPU) has been introduced an alternative of conventional CPU for highly parallel computing applications both for general purpose and graphic processing. Rather than using the traditional way of coding algorithms in serial by single CPU, many multithreading programming models has been introduced such as CUDA, OpenMP, and MPI to make parallel processing by using multicores. These parallel programming models are supportive to data driven multithreading (DDM) principle [3]. In this paper, we have presented performance based preliminary evaluation of these programming models and compared with the conventional single CPU serial processing system. We have implemented a massive computational operation for performance evaluation such as complex matrix multiplication operation. We used data driven multithreaded HPC system for performance evaluation and presented the results with a comprehensive analysis of these parallel programming models for HPC parallelism.

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Evaluation of Performance on Open MP Parallel Platform based on Problem Size

By Yajnaseni Dash Sanjay Kumar V.K. Patle

DOI: https://doi.org/10.5815/ijmecs.2016.06.05, Pub. Date: 8 Jun. 2016

This paper evaluates the performance of matrix multiplication algorithm on dual core 2.0 GHz processor with two threads. A novel methodology was designed to implement this algorithm on Open MP platform by selecting time of execution, speed up and efficiency as performance parameters. Based on the experimental analysis, it was found that a good performance can be achieved by executing the problem in parallel rather than sequential after a certain problem size.

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Game Theory - basis of Higher Education and Teaching Organization

By Guram N. Beltadze

DOI: https://doi.org/10.5815/ijmecs.2016.06.06, Pub. Date: 8 Jun. 2016

The process of effective interrelation necessary for teaching the subject at higher school has been represented as a noncooperative game between the professor and the students. This process is the functioning of teaching of organizational  system which comprises -pedagogue (professor) and -collective of students. The preference is given to the democratic model of relation - to objective and optimal mutual responsibility of the pedagogue and a student to the rights-obligations imposed on them. Two classes of models of noncooperatve games corresponding to management of  system have been built - games with relations of preferences and the games with utility. The main principle of optimality is the Nash equilibrium, or it is such kind of situation, none of the player it is not profitable the unilateral deviation from it. According to the indicated principle of equilibrium the tasks originated in the process of  system functioning has been solved. According to the solving results students must study systamatically do their tasks and teachers must be responsible objective for their work.

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Digital Forensics through Application Behavior Analysis

By Shuaibur Rahman M. N. A. Khan

DOI: https://doi.org/10.5815/ijmecs.2016.06.07, Pub. Date: 8 Jun. 2016

The field of digital forensic analysis has emerged in the past two decades to counter the digital crimes and investigate the modus operandi of the culprits to secure the computer systems. With the advances in technologies and pervasive nature of the computing devices, the digital forensic analysis is becoming a challenging task. Due to ease of digital equipment and popularity of Internet, criminals have been enticed to carry out digital crimes. Digital forensic is aimed to investigate the criminal activity and bring the culprits to justice. Traditionally the static analysis is used to investigate about an incident but due to a lot of issues related the accuracy and authenticity of the static analysis, the live digital forensic analysis shows an investigator a more complete picture of memory dump. In this paper, we introduce a module for profiling behavior of application programs. Profiling of application is helpful in forensic analysis as one can easily analyze the compromised system. Profiling is also helpful to the investigator in conducting malware analysis as well as debugging a system. The concept of our model is to trace the unique process name, loaded services and called modules of the target system and store it in a database for future forensic and malware analysis. We used VMware workstation version 9.0 on Windows 7 platform so that we can get the detailed and clean image of the current state of the system. The profile of the target application includes the process name, modules and services which are specific to an application program.

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A Review of NBTI Degradation and its Impact on the Performance of SRAM

By Umesh Dutta M.K Soni Manisha Pattanaik

DOI: https://doi.org/10.5815/ijmecs.2016.06.08, Pub. Date: 8 Jun. 2016

Temporal degradation of VLSI design is a major reliability concern for highly scaled silicon IC technology. Negative Bias Temperature Instability (NBTI) in particular is a serious threat affecting the performance of both digital and analog circuits with time. This paper presents a review of NBTI degradation, its mechanism and various factors that affect the degradation caused by NBTI. Reaction Diffusion (RD) model based analytical expressions developed by various researchers are also discussed along with their features and underlying assumptions. Degradation in the Static RAM (SRAM) performance caused by NBTI is also discussed in detail along with the strategies that are employed to combat the effect of NBTI degradation in SRAM. Results of the review done for SRAM cell under NBTI degradation suggests that these design strategies are effective in improving the SRAM cell performance.

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