Naresh Grover; M.K.Soni

Reduction of Power Consumption in FPGAs - An Overview

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Author(s)

Naresh Grover ^1,* M.K.Soni ¹

1. Faculty of Engineering and Technology, Manav Rachna International University, Faridabad, India

* Corresponding author.

DOI: https://doi.org/10.5815/ijieeb.2012.05.07

Received: 10 Jun. 2012 / Revised: 25 Jul. 2012 / Accepted: 3 Sep. 2012 / Published: 8 Oct. 2012

Index Terms

Static and dynamic power, embedded memories, body biasing, clock gating, glitches, logic power, soft processors

Abstract

Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. In more than 20 years since the introduction of FPGA, research and development has produced dramatic improvements in FPGA speed and area efficiency, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. FPGAs hold significant promise as a fast to market replacement. Unfortunately, the advantages of FPGAs are offset in many cases by their high power consumption and area. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. This paper presents the tips to lower down the static and dynamic power dissipation in FPGAs. It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.

Cite This Paper

Naresh Grover, M.K.Soni, "Reduction of Power Consumption in FPGAs - An Overview", International Journal of Information Engineering and Electronic Business(IJIEEB), vol.4, no.5, pp.50-69, 2012. DOI:10.5815/ijieeb.2012.05.07

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