Work place: Computer Science and Information Technology, West Pomeranian University of Technology, Szczecin, Poland
Research Interests: Image Processing, Computer systems and computational processes, Signal Processing, Graph and Image Processing, Data Structures and Algorithms
Aleksandr Cariow, received the Candidate of Sciences and Doctor of Sciences degrees (Habilitation) in Computer Sciences from LITMO of St. Petersburg, Russia in 1984 and 2001. In September 1999, he joined the Faculty of Computer Sciences and Information Technology, at the West Pomeranian University of Technology, Szczecin, Poland, where he is currently a Professor and Chair of the Department of Computer Architectures and Telecommunications. His research interests include digital signal and image processing and transmission, fast computational algorithms, DSP VLSI architectures, and data processing parallelization.
DOI: https://doi.org/10.5815/ijigsp.2014.10.01, Pub. Date: 8 Sep. 2014
In this paper two different approaches to the rationalization of FDWT and IDWT basic operations execution with the reduced number of multiplications are considered. With regard to the well-known approaches, the direct implementation of the above operations requires 2L multiplications for the execution of FDWT and IDWT basic operation plus 2(L-1) additions for FDWT basic operation and L additions for IDWT basic operation. At the same time, the first approach allows the design of the computation procedures, which take only 1,5L multiplications plus 3,5L+1 additions for FDWT basic operation and L+1 multiplications plus 3,5L additions for IDWT basic operation. The other approach allows the design of such computation procedures, which require 1,5L multiplications, plus 2L-1 addition for FDWT basic operation and L+1 addition for IDWT basic operation.[...] Read more.
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