The major disadvantage of a standard bus topology is the constraint of being able to realize only one communication at a time (the tasks may take place in parallel but the communications are only done in a sequential). As these communications are handled by the bus arbiter, a Bottleneck when the number of communications increases, but also when the bandwidth constraints of several communications become important.This arbitration plays a predominant role because it authorizes communications on the bus but it is also in charge of resolving the conflicts (several requests of communications at the same time). This arbitration implies therefore a limitation on the number of IP connected to the bus to a dozen elements.
This work elaborates the AMBA bus interface with four masters interacting with single memory system, using Arbiter between memory controller and other supporting peripherals. Different module of i.e., AHB MSTER, AHB SLAVE INTERFACE AND AHB ARBITER(round robin algorithm)has been developed with VHDL. Further integration with FIFO, RAM and ROM with memory controller is done. The Four AHB master initiates the operations and generates the necessary control signals on single bus to memory controller with the help of arbiter. The proposed architecture shows the area efficient management as compared to previous researches of multiple data communication in AHB BUS system. The system model is synthesized with Xilinx XC6vx75t-2ff484 and simulated with MODELSIM.

This paper elaborates the AMBA bus interface bridge between memory controller and other supporting peripheral. The work claims the integration with FIFO, RAM and ROM with slave interface and the master of AHB bus. The AHB master initiates the operation and generates the necessary control signal. Memory controller is implemented with finite state machine considering with all the peripheral works in synchronous mode. Despite these shortcomings of the work performed study and development that followed has led the development of a memory controller on AMBA-AHB bus at a very advanced stage and next to prototyping. VHDL code is utilized to develop the design and it is synthesized in Xilinx Virtex 6 device (XC6VCX75T). The design claims a minor area overhead with improvement in speed 185.134 MHz.

As the technology era has been changing, the designing pattern of an IC is also changing. An IC de-signing is now divided into two definite fields i.e. Front-End design and Back-End design. The Front-End design is using HDLs (Hardware Description Languages i.e. VHDL or Verilog) and the verification of those ICs, whereas the Back-End Design is related to the Physical Design techniques. But both of the IC design techniques required some extra efforts in terms of their Speed, Shape, and Size, which needs the Optimization efforts. This pa-per deals with the area and power optimization efforts in terms of the logic utilization by using XST & Vivado Tools. After applying area optimization techniques i.e. Logic Optimization, LUT mapping and Resource Sharing etc. on already designed asynchronous microprocessor to be used as model for proposed optimization, reasonable results in terms of power and area utilization have been achieved.

In today’s fast growing world, the digital design domain has two dominant role factors i.e. the efficiency and speed. The design of asynchronous processor is used to reduce the various challenges faced in synchronous architectures. There are numerous advantages of asynchronous processors, especially in SOC (System on the chip), reducing the crosstalk between analog and digital circuits, easiness in multi-rate circuit integration, reusability of ease of component and at last the less power consumption. The objective of this research paper is to design and simulate control unit of the asynchronous processor by using Xilinx ISE tool in VHDL. A robust control unit has been designed using FPGA. This control unit is responsible for accumulating the whole processor functioning control at a single unit. This paper further presents the optimization techniques for reducing area power and delay constraints related to digital circuits using FPGA.

As the efficiency and power consumption plays an important role in electronic system design, an asynchronous design is used to reduce such challenges faced in synchronous architectures. The asynchronous processors have a number of advantages, especially in SoC (System on chip) including reduced crosstalk between analog and digital circuits, ease of integrating multi-rate circuits, ease of component reuse and less power consumption as well. This paper deals with the novel design and implementation of such type of asynchronous microprocessor by using VHDL on Xilinx ISE tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time.

Electrocardiogram (ECG) is very crucial and important tool to detect the cardiac problems. For ECG analysis, it is essential to measure ECG parameter accurately. It is very critical in all types of ECG application. The accurate R Peaks detection is starting step in extracting ECG features which is necessary for the other ECG performance stages. It is very essential to detect these R-peaks accurately and efficiently to detect heart diseases or anomalies which create primary source of death in the universe. Hence automatic R-peaks detection in a lengthy duration ECG signal is very meaningful to diagnose the cardiac disorders. Here a latest R-peak exposure algorithm depended on Shannon energy envelope estimator and logic to find peaks has been proposed which uses the simple threshold of Shannon energy.

This paper studies on image registration using Ant Colony Optimization technique of the medical imag-es. Ant Colony Optimization algorithm has ability of global optimization and facilitates quick search of opti-mal parameters for image registration. In this paper, a modified Ant Colony Optimization algorithm on prepro-cessed images is proposed to improve the accuracy in terms of PSNR (peak signal to noise ratio), Entropy and convergence speed. Preprocessing of images is adopted to remove noise so that extracted features provide more accurate and precise information about the image and results are more suitable for further analysis. The experi-mental results demonstrate the performance of proposed methodology as compared with traditional approaches as very promising.

Simulations and prototyping have been a very important part of the electronics industry since a very long time. In recent years, FPGA's have become increasingly important and have found their way into all kind of digital system design This paper presents a novel, easy and efficient approach of implementation and verification of VHDL code using Simulink and then to regenerate the optimized VHDL code again using Simulink. The VHDL code written for the complicated digital design of 32-bit floating point arithmetic unit has been synthesized on Xilinx, verified and simulated on Simulink. The same VHDL code in Modelsim was optimized using this approach and the optimized code so generated by Simulinkhas also been synthesized to compare the results. Power dissipations for both synthesized designs using Xilinx Power Estimator were also extracted for comparison.

Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources than integer operations. With the current trends in system requirements and available FPGAs, floating-point implementations are becoming more common and designers are increasingly taking advantage of FPGAs as a platform for floating-point implementations. The rapid advance in Field-Programmable Gate Array (FPGA) technology makes such devices increasingly attractive for implementing floating-point arithmetic. Compared to Application Specific Integrated Circuits, FPGAs offer reduced development time and costs. Moreover, their flexibility enables field upgrade and adaptation of hardware to run-time conditions. A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, subtraction, multiplication and division are tested on Xilinx. Thereafter, Simulink model in MAT lab has been created for verification of VHDL code of that Floating Point Arithmetic Unit in Modelsim.

Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. In more than 20 years since the introduction of FPGA, research and development has produced dramatic improvements in FPGA speed and area efficiency, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. FPGAs hold significant promise as a fast to market replacement. Unfortunately, the advantages of FPGAs are offset in many cases by their high power consumption and area. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. This paper presents the tips to lower down the static and dynamic power dissipation in FPGAs. It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.