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Charu Rana

Work place: ITM University/Department of EECE, Gurgaon, 122001, India

E-mail: charurana@itmindia.edu

Website:

Research Interests: Computational Science and Engineering, Engineering

Biography

Charu rana was born in Itanagar, Arunachal Pradesh on 1984. She recieved her B.Tech degree in Electronics and Communication Engineering from Kurukshetra University in 2005 and M.Tech in VLSI Design from Mody Instiute of Technology and Science, Sikar in 2008. She is currently involved in Ph.D work in Jamia Millia Islamia. Her area of research is Low Power Design Techniques. She is currently working as Assistant Professor, Senior Scale in ITM University, Gurgaon, Haryana, India.

Author Articles
Design of Low Power Sequential Circuit by using Adiabatic Techniques

By Priyanka Ojha Charu Rana

DOI: https://doi.org/10.5815/ijisa.2015.08.06, Pub. Date: 8 Jul. 2015

Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a better energy saving techniques then ECRL logic circuit.

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