S.A. Gholamian

Work place: Faculty of electrical engineering, Babol University, Iran

E-mail: gholamian@nit.ac.ir

Website:

Research Interests: Computational Science and Engineering, Engineering

Biography

Seyed Asghar Gholamian received B.S degree from khaje nasiredin toosi university of technology in 1999,and received M.S degree university of mazandaran in 2001,recieved PhD degree from khaje nasiredin toosi university of technology 2009,faculty member of babol university of technology, babol, Iran. His research interests are:

  • Design, simulation, modeling and control of electrical machines
  • Condition monitoring and fault diagnosis of electric machinery
  • Electric and Hybrid Electric Vehicles motor
  • Power converters for electric machines
  • Simulation techniques such as finite elements analysis and MATLAB
  • Novel electric machines for different applications
  • Renewable Energy

Author Articles
Optimal Placement and Sizing of Capacitor and Distributed Generation with Harmonic and Resonance Considerations Using Discrete Particle Swarm Optimization

By M. Heydari S.M. Hosseini S.A. Gholamian

DOI: https://doi.org/10.5815/ijisa.2013.07.06, Pub. Date: 8 Jun. 2013

Presence of distributed generation (DG) in distribution systems has significant impacts on the operational characteristics of these systems, also using capacitor for reactive compensation and loss reduction is so common. Injected harmonic currents from non-linear loads into distribution system distort all of voltages and currents and must be considered when placing the capacitor banks so that the resonance will not occur. In this paper discrete particle swarm optimization (DPSO) approach is used for the optimal placement and sizing of distributed generations and capacitors in distribution systems for simultaneous voltage profile improvement, loss and total harmonic distortion (THD) reduction. There is a term in the objective function which prevents harmonic resonance between capacitor reactance and system reactance. Constraints include voltage limit, voltage THD, number/ size of capacitors and generators. For evaluating the proposed algorithm, the IEEE 33-bus test system is modified and employed.

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