Bhavana Jharia

Work place: Dept. of Electronics & Communication Engg. Jabalpur Engineering College, Jabalpur, India

E-mail: dr.bhavana.jharia@jec-jabalpur.org

Website:

Research Interests: Interaction Design, Computer systems and computational processes, Processor Design, Data Structures and Algorithms, Algorithm Design, Logic Calculi

Biography

Bhavana Jharia is presently working as a Associate professor in Department of Electronics & Communication Engineering, Jabalpur Engineering College, Jabalpur, (M. P.), INDIA. Dr. B. Jharia received B.E. degree from Government Engineering College, Jabalpur in 1987 , M.E. from UOR, Roorkee in 1998 and Ph. D. Degrees from I.I.T. Roorkee in 2008. She has published more than 40 research papers in national, International Journals and supervised 30 B.E. 20 M.E. thesis in the area of VLSI design, Communication etc. She is a member of IEEE, IE (I), CSI, VLSI Society of India, senior member of IACSIT and Life Member of ISTE. She has been the coordinator, National Mission on Education through ICT conducted by I.I.T. Bombay. She is a member of editorial board and reviewer of many International Journals and Conferences. The main interest of her current work includes VLSI Design, Communication, Wireless communication and Fuzzy Logic.

Author Articles
FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller

By Vinod Kapse Bhavana Jharia S. S. Thakur

DOI: https://doi.org/10.5815/ijmecs.2012.07.04, Pub. Date: 8 Jul. 2012

This paper presents a high-speed VLSI fuzzy inference processor for the real-time applications using trapezoid-shaped membership functions. Analysis shows that the matching degree between two trapezoid-shaped membership functions can be obtained without traversing all the elements in the universal disclosure set of all possible conditions. A FPGA based pipelined parallel VLSI architecture has been proposed to take advantage of this basic idea, implemented on CycloneII-EP2C70F896C8. The controller is capable of processing fuzzified input. 
The proposed controller is designed for 2-input 1-output with maximum clock rate is 12.96 MHz and 275.33 MHz for 16 and 8 rules respectively. Thus, the inference speed is 0.81 and 34.41 MFLIPS for 16 and 8 rules, respectively.

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